SPI Flash Chip - SST(25VF040B) Command List

DEVICE OPERATION INSTRUCTIONS

Instruction	Description	Op Code Cycle 1	Address Cycle(s) 2	Dummy Cycle(s)	Data Cycle(s)	Maximum Frequency
Read	Read Memory at 25 MHz	0000 0011b (03H)	3	0	1 to ∞	25 MHz
High-Speed Read	Read Memory at 50 MHz	0000 1011b (0BH)	3	1	1 to ∞	50 MHz
4 KByte Sector-Erase 3	Erase 4 KByte of memory array	0010 0000b (20H)	3	0	0	50 MHz
32 KByte Block-Erase 4	Erase 32 KByte block of memory array	0101 0010b (52H)	3	0	0	50 MHz
64 KByte Block-Erase 5	Erase 64 KByte block of memory array	1101 1000b (D8H)	3	0	0	50 MHz
Chip-Erase	Erase Full Memory Array	0110 0000b (60H) 1100 0111b (C7H)	0	0	0	50 MHz
Byte-Program	To Program One Data Byte	0000 0010b (02H)	3	0	1	50 MHz
AAI-Word-Program 6	Auto Address Increment Programming	1010 1101b (ADH)	3	0	2 to ∞	50 MHz
RDSR 7	Read-Status-Register	0000 0101b (05H)	0	0	1 to ∞	50 MHz
EWSR	Enable-Write-Status-Register	0101b 0000b (50H)	0	0	0	50 MHz
WRSR	Write-Status-Register	0000 0001b (01H)	0	0	1	50 MHz
WREN	Write-Enable	0000 0110b (06H)	0	0	0	50 MHz
WRDI	Write-Disable	0000 0100b (04H)	0	0	0	50 MHz
RDID 8	Read-ID	1001 0000b (90H) 1010 1011b (ABH)	3	0	1 to ∞	50 MHz
JEDEC-ID	JEDEC ID read	1001 1111b (9FH)	0	0	3 to ∞	50 MHz
EBSY	Enable SO to output RY/BY# status during AAI programming	0111 0000b (70H)	0	0	0	50 MHz
DBSY	Disable SO to output RY/BY# status during AAI programming	1000 0000b (80H)	0	0	0	50 MHz

1. One bus cycle is eight clock periods.

2. Address bits above the most significant bit of each density can be VIL or VIH.

3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.

4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.

5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.

6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0=1.

7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.

JEDEC READ-ID DATA

Manufacturer’s ID	Device ID
	Memory Type	Memory Capacity
Byte 1	Byte 2	Byte 3
BFH	25H	8DH

PRODUCT IDENTIFICATION

	Address	Data
Manufacturer’s ID	00000H	BFH
Device ID SST25VF040B	00001H	8DH