POST Memory Manager(PMM) get temporary memory in PCI FW3.0

5.2.1.24.1. Executing the Expansion ROM Configuration Code
The configuration code remains in temporary memory so long as it is possible that an end user may
need to use the configuration code.  The system firmware will make a far call into the configuration
utility code, and the configuration utility will perform a far return to pass control back to system
firmware when it has completed.  The configuration code need not preserve any registers, and is
expected to update the BH register as defined below.  The system firmware will call the
configuration code in “Big Real Mode”, as defined in the footnote to Section  5.2.1.9.  In addition,
the Bus/Device/Function number and the far pointer to the PMM entry point will be provided as
argument as shown below.
Arg.     Register          Meaning
1          [AH]      Bus number
2          [AL]       Upper 5 bits are the Device number
3          [AL]       Lower 3 bits are the Function number 
4          [BL]       System Firmware state:
      Bit 0 set = BIOS is performing Console Redirection.
      Bit 1-7 = Reserved.
5          [BH]      Configuration utility status.  Cleared to zero by system firmware prior to call. 
6          [CX]      Segment of the PMM Services Entry Point.
7          [DX]      Offset of the PMM Services Entry Point.  
8          [SI]        Segment of the run-time Expansion ROM code.
9          [DI]       Offset of the run-time Expansion ROM code. 
Prior to returning control to the system firmware via a far return, the configuration code will update
the BH register as follows:
    Bit 0 set = Configuration utility is requesting a system reset
    Bit 1-7 = Reserved 
The system firmware provides the far pointer to the PMM Services Entry point.  The PMM Services
Entry pointer is described in Section 3.1.1 “PMM Structure”, (offset 7) of the POST Memory Manager
Specification, Version 1.01.  By providing the PMM Services Entry pointer, it is no longer necessary for
the Expansion ROM code to search for the PMM Structure, validate the PMM signature, and
validate the PMM checksum.
The configuration utility code can assume that all basic devices have been initialized and the system
firmware is providing input and output services.  The configuration utility code must use the system
firmware Interrupt services for input and output functions.
System firmware will have a list of all the configuration code from the various Expansion ROMs. 
System firmware will be responsible for creating a method for the end user to selectively execute the configuration code.  This may be done within a specific page of the ROM based Setup program. 
However, the exact method for selecting and executing the individual Option ROM configuration
code is not defined by this specification.

5.2.1.2.    POST Firmware Extensions
The POST firmware copies the entire Expansion ROM image into a RAM address, as described above.  The RAM address can vary depending on whether the Expansion ROM identifies itself as being PCI Firmware 3.0 Specification compliant.  (A value of 03h in the PCI Data Structure Revision field indicates compliance.)
If the Expansion ROM is compliant, then the following steps will be followed by the POST Firmware:
1.   POST Firmware will place the Expansion ROM in RAM at an address that may not be the final run-time execution address.  This address will be below the 1-MB address boundary.
2.   The POST firmware will then call the INIT function entry point and supply the six arguments
described in Table 5-2.
3.   As part of the INIT function, the Expansion ROM code must place the final run-time Expansion ROM image into the run-time address provided by the POST firmware. Note that the Expansion ROM code must ensure that the device is quiescent until the interrupt service routine is in place at the final run-time location.  Caution must be taken in chaining the interrupt service routine.  It is possible that an interrupt may arrive while the interrupt service routine is being installed.
4.   The POST Firmware will not write-protect the RAM containing the run-time Expansion ROM code at this step.  In a PCI Firmware 3.0 compliant system, the write-protection step will be delayed until the Setup portion of the Expansion ROM code, if any, has been executed.
5.   The POST firmware will erase the old image from the temporary RAM location.


Table  5-2:  Arguments for a PCI 3.0 Compatible Expansion ROM
Argument Number    Register           Meaning
1  [AH]           Bus number
2  [AL]           Upper 5 bits are the Device number
3  [AL]           The lower 3 bits are the Function number
4  [BX]           Run-time address.  This is the final run-time address where the ROM image will be located after Initialization.  This address is in units of 16-bytes.
5  [CX]           Segment of the PMM Services Entry Point
6  [DX]           Offset of the PMM Services Entry Point

Table  5-3:  Arguments for a Legacy Expansion ROM
Argument Number    Register           Meaning
1  [AH]           Bus number
2  [AL]           Upper 5 bits are the Device number
3  [AL]           The lower 3 bits are the Function number

If the Expansion ROM is not compliant with the PCI 3.0 Firmware Specification, then the following steps will be followed by the POST Firmware:
1.   POST Firmware will place the Expansion ROM in RAM within the legacy compatibility address (usually 0C0000h to 0E0000h).
2.   The POST firmware will then call the INIT function entry point and supply the three arguments described in Table 5-3.
3.   The POST Firmware will then write-protect the RAM containing the run-time Expansion ROM code.  The size of the Expansion ROM and amount of RAM to write-protect is determined by examining the Current Image Size field at offset 2 in the ROM header.
The POST firmware should be prepared to handle any mixture of Revision 3.0 compliant and non-
complaint Expansion ROMs in the system.