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2012年5月30日 星期三

SMART DISABLE OPERATIONS - B0h/D9h, Non-data


Inputs:
Register
7
6
5
4
3
2
1
0
Features
D9h
Sector Count
na
LBA Low
na
LBA Mid
4Fh
LBA High
C2h
Device
obs
na
obs
DEV
na
na
na
na
Command
B0h

Normal Outputs:
Register
7
6
5
4
3
2
1
0
Error
na
Sector Count
na
LBA Low
na
LBA Mid
na
LBA High
na
Device
obs
na
obs
DEV
na
na
na
na
Status
BSY
DRDY
DF
na
DRQ
na
na
ERR

Error Outputs:
Register
7
6
5
4
3
2
1
0
Error
na
na
na
na
na
ABRT
na
na
Sector Count
na
LBA Low
na
LBA Mid
na
LBA High
na
Device
obs
na
obs
DEV
na
Status
BSY
DRDY
DF
na
DRQ
na
na
ERR
Device register -
DEV shall indicate the selected device.
Status register -
BSY shall be cleared to zero indicating command completion.
DRDY shall be set to one.
DF (Device Fault) shall be cleared to zero.
DRQ shall be cleared to zero.
ERR shall be cleared to zero.

2012年5月28日 星期一

SMP functions


SMP(Serial Management Protocol)
Code
SMP Function
00h
Report General
01h
Report Manufacturer Information
02h
Read GPIO Register(See SFF-8485)(SAS2)
03h
Report Zone Permission(SAS2)
10h
Discovery
11h
Report Phy Error Log
12h
Report Phy SATA
13h
Report Route Information
14h
Report Phy Event Information(SAS2) or
Report Zone Route Table(SAS2)
40h-7Fh
Vendor specific read type functions
80h
Configure General(SAS2)
82h
Write GPIO Register(See SFF-8485)(SAS2)
83h
Configure Zone Permission(SAS2)
84h
Active Supervisor Update(SAS2)
90h
Configure Route Information
92h
Phy Test Function(SAS2)
93h
Configure Zone Phy(SAS2)
C0h-FFh
Vendor specific write type functions
All Others
Reserved for SAS Committee

2012年5月24日 星期四

SMART Feature register values


Value
Command
00h-CFh
Reserved
D0h
SMART READ DATA
D1h
Obsolete
D2h
SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE
D3h
Obsolete
D4h
SMART EXECUTE OFF-LINE IMMEDIATE
D5h
SMART READ LOG
D6h
SMART WRITE LOG
D7h
Obsolete
D8h
SMART ENABLE OPERATIONS
D9h
SMART DISABLE OPERATIONS
DAh
SMART RETURN STATUS
DBh
Obsolete
DCh-DFh
Reserved
E0h-FFh
vendor specific

2012年5月21日 星期一

Expansion ROM Base Address Register


6.2.5.2.   Expansion ROM Base Address Register

Some PCI devices, especially those that are intended for use on add-in cards in PC architectures, require local EPROMs for expansion ROM (refer to Section 6.3. for a definition of ROM contents).  The four-byte register at offset 30h in a type 00h predefined header is defined to handle the base address and size information for this expansion ROM.  Figure 6-7 shows how this word is organized.  The register functions
exactly like a 32-bit Base Address register except that the encoding (and usage) of the bottom bits is different.  The upper 21 bits correspond to the upper 21 bits of the Expansion ROM base address.  The number of bits (out of these 21) that a device actually implements depends on how much address space the device requires.  For instance, a device that requires a 64 KB area to map its expansion ROM would implement the top 16 bits in the register, leaving the bottom 5 (out of these 21) hardwired to 0.  Devices that
support an expansion ROM must implement this register.

Device independent configuration software can determine how much address space the device requires by writing a value of all 1's to the address portion of the register and then reading the value back.  The device will return 0's in all don't-care bits, effectively specifying the size and alignment requirements.  The amount of address space a device requests must not be greater than 16 MB.

Bit 0 in the register is used to control whether or not the device accepts accesses to its expansion ROM.  When this bit is 0, the device’s expansion ROM address space is disabled.  When the bit is 1, address decoding is enabled using the parameters in the other part of the base register.  This allows a device to be used with or without an expansion ROM depending on system configuration.  The Memory Space bit in the Command register has precedence over the Expansion ROM enable bit.  A device must respond to accesses to its expansion ROM only if both the Memory Space bit and the Expansion ROM Base Address Enable bit are set to 1.  This bit's state after RST# is 0.

In order to minimize the number of address decoders needed, a device may share a decoder between the Expansion ROM Base Address register and other Base Address registers.When expansion ROM decode is enabled, the decoder is used for accesses to the expansion ROM and device independent software must not access the device through any other Base Address registers.