Int1Ah AX = B10Ah(在PCI表面配置空間上，讀取DWord) -- BIOS Int1Ah

READ CONFIGURATION DWORD

Input:

AX = B10Ah
BH = bus number
BL = device/function number (bits 7-3 device, bits 2-0 function)
DI = register number (0000h-00FFh, must be multiple of 4) (see PCI Configuration Data Format)
Return: 
CF clear if successful
   ECX = dword read
CF set on error
AH = status (00h,87h) (see PCI BIOS v2.0 status codes)
EAX, EBX, ECX, and EDX may be modified

all other flags (except IF) may be modified
Notes:

this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call

the meanings of BL and BH on entry were exchanged between the initial drafts of the specification and final implementation

BUG:

the Award BIOS 4.51PG (dated 05/24/96) incorrectly returns FFFFFFFFh for register 00h if the PCI function number is nonzero

Int1Ah AX = B109h(在PCI表面配置空間上，讀取Word) -- BIOS Int1Ah

READ CONFIGURATION WORD

Input:
AX = B109h
BH = bus number
BL = device/function number (bits 7-3 device, bits 2-0 function)
DI = register number (0000h-00FFh, must be multiple of 2) (see PCI Configuration Data Format)
Return: 
 CF clear if successful
   CX = word read
CF set on error
AH = status (00h,87h) (see PCI BIOS v2.0 status codes)
EAX, EBX, ECX, and EDX may be modified
all other flags (except IF) may be modified
Notes:

this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call

the meanings of BL and BH on entry were exchanged between the initial drafts of the specification and final implementation

BUG:

the Award BIOS 4.51PG (dated 05/24/96) incorrectly returns FFFFh for register 00h if the PCI function number is nonzero

Int1Ah AX = B108h(在PCI表面配置空間上，讀取Byte) -- BIOS Int1Ah

READ CONFIGURATION BYTE


Input:
AX = B108h
BH = bus number
BL = device/function number (bits 7-3 device, bits 2-0 function)
DI = register number (0000h-00FFh) (see PCI Configuration Data Format)
Return: 
        CF clear if successful
   CL = byte read
CF set on error
AH = status (00h,87h) (see PCI BIOS v2.0 status codes)
EAX, EBX, ECX, and EDX may be modified
all other flags (except IF) may be modified
Notes:

this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call the meanings of BL and BH on entry were exchanged between the initial drafts of the specification and final implementation

BUG:

the Award BIOS 4.51PG (dated 05/24/96) incorrectly returns FFh for register 00h if the PCI function number is nonzero

PCI表面配置資料格式

Format of PCI Configuration Data:

Offset Size Description
 00h WORD vendor ID (read-only)
FFFFh returned if requested device non-existent
 02h WORD device ID (read-only)
 04h WORD command register
 06h WORD status register
 08h BYTE revision ID
 09h  3 BYTEs class code
bits 7-0: programming interface
bits 15-8: sub-class
bits 23-16: class code
 0Ch BYTE cache line size

 0Dh BYTE latency timer
 0Eh BYTE header type
bits 6-0: header format
00h other
01h PCI-to-PCI bridge
02h PCI-to-CardBus bridge
bit 7: multi-function device
 0Fh BYTE Built-In Self-Test result
---header type 00h---
 10h DWORD base address 0
(OpenHCI) base address of host controller registers
 14h DWORD base address 1
 18h DWORD base address 2
 1Ch DWORD base address 3

 20h DWORD base address 4
 24h DWORD base address 5
 28h DWORD CardBus CIS pointer (read-only)
 2Ch WORD subsystem vendor ID or 0000h
 2Eh WORD subsystem ID or 0000h
 30h DWORD expansion ROM base address
 34h BYTE offset of capabilities list within configuration space (R/O)
(only valid if status register bit 4 set)
 35h  3 BYTEs reserved
 38h DWORD reserved
 3Ch BYTE interrupt line

00h = none, 01h = IRQ1 to 0Fh = IRQ15
 3Dh BYTE interrupt pin (read-only)
(00h = none, else indicates INTA# to INTD#)
 3Eh BYTE minimum time bus master needs PCI bus ownership, in 250ns units
(read-only)
 3Fh BYTE maximum latency, in 250ns units (bus masters only) (read-only)
 40h 48 DWORDs varies by device
---header type 01h---
 10h DWORD base address 0

 14h DWORD base address 1
 18h BYTE primary bus number (for bus closer to host processor)
 19h BYTE secondary bus number (for bus further from host processor)
 1Ah BYTE subordinate bus number
 1Bh BYTE secondary latency timer
 1Ch BYTE I/O base
 1Dh BYTE I/O limit
 1Eh WORD secondary status
 20h WORD memory base
 22h WORD memory limit
 24h WORD prefetchable memory base

 26h WORD prefetchable memory limit
 28h DWORD prefetchable base, upper 32 bits
 2Ch DWORD prefetchable limit, upper 32 bits
 30h WORD I/O base, upper 16 bits
 32h WORD I/O limit, upper 16 bits
 34h DWORD reserved
 38h DWORD expansion ROM base address
 3Ch BYTE interrupt line
 3Dh BYTE interrupt pin (read-only)
 3Eh WORD bridge control
 40h 48 DWORDs varies by device

PCI BIOS 2.0狀態表

Values for PCI BIOS v2.0c+ status codes:


 00h successful
 81h unsupported function
 83h bad vendor ID
 86h device not found
 87h bad PCI register number

Int1Ah AX = B106h(PCI匯流排特殊的操作) -- BIOS Int1Ah

PCI BUS-SPECIFIC OPERATIONS


Input:
AX = B106h
BL = bus number
EDX = Special Cycle data

Return: 
 CF clear if successful
CF set on error
AH = status (00h,81h) (see Format of floppy format address field buffer entry)
EAX, EBX, ECX, and EDX may be modified
all other flags (except IF) may be modified

Note:

this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call

Read/Write PCI configuration space by I/O port

/*Read PCI configuration space by I/O port*/
u32 read_pci_cfg_u32(u8 bus, u8 dev, u8 fun, u8 regs)
{
u32 reg_offset, value = 0;
reg_offset = (u32)(0x80000000L | (u32)bus << 16 | (u32)dev << 11 | (u32)fun << 8 | (u32)regs);
__asm{
pushad 
mov eax, reg_offset
mov dx, 0CF8h 
out dx, eax 

mov dx, 0CFCh 
in eax, dx 
mov value, eax
popad 
}
return value;
}

/*Write PCI configuration space by I/O port*/

void write_pci_cfg_u32(u8 bus, u8 dev, u8 fun, u8 regs, u32 value)
{
u32 reg_offset;
reg_offset = (u32)(0x80000000L | (u32)bus << 16 | (u32)dev << 11 | (u32)fun << 8 | (u32)regs);
__asm{
pushad 
mov eax, reg_offset
mov dx, 0CF8h 
out dx, eax 

mov eax, value
mov dx, 0CFCh
out dx, eax 
popad 
}
}

Int1Ah AX = B103h(搜尋PCI類別碼) -- BIOS Int1Ah

FIND PCI CLASS CODE

Input:
    AX = B103h
    ECX = class code
        bits 31-24 unused
        bits 23-16 class
        bits 15-8  subclass
        bits 7-0   programming interface
    SI = device index (0-n)
Return: 
    CF clear if successful
    CF set on error
    AH = status (00h,86h) (see Format of floppy format address field buffer entry)
        00h successful
        BH = bus number
        BL = device/function number (bits 7-3 device, bits 2-0 func)
        86h device not found
    EAX, EBX, ECX, and EDX may be modified

all other flags (except IF) may be modified

Notes:  

• this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call

• the meanings of BL and BH on return were exchanged between the initial drafts of the specification and final implementation

• all devices sharing the same Class Code may be enumerated byincrementing SI from 0 until error 86h is returned

Int1Ah AX = B102h(搜尋PCI裝置) -- BIOS Int1Ah

FIND PCI DEVICE

Input:
    AX = B102h
    CX = device ID
    DX = vendor ID (Intel:0x8086, MRVL:0x1B4B, Acer:0x1025, AMI:0x101E, Phoenix:0x100A)
    SI = device index (0-n)
Return:
    CF clear if successful
    CF set on error
    AH = status (00h,83h,86h)  (see Format of floppy format address field buffer entry)
        00h successful
        BH = bus number
        BL = device/function number (bits 7-3 device, bits 2-0 func)
    EAX, EBX, ECX, and EDX may be modified

all other flags (except IF) may be modified

Notes:   

• this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call
• device ID FFFFh may be reserved as a wildcard in future implementations
• the meanings of BL and BH on return were exchanged between the initial
• drafts of the specification and final implementation
• all devices sharing a single vendor ID and device ID may be enumerated by incrementing SI from 0 until error 86h is returned

SPI Flash Chip - Numonyx(M25PX80) Command List

Features

> SPI bus compatible serial interface

> 75 MHz (maximum) clock frequency

> 2.3 V to 3.6 V single supply voltage

> Dual input/output instructions resulting in an equivalent clock frequency of 150 MHz:

-        Dual Output Fast Read instruction

-        Dual Input Fast Program instruction

>  8 Mbit Flash memory

-        Uniform 4-Kbyte subsectors

-        Uniform 64-Kbyte sectors

> Additional 64-byte user-lockable, one-time programmable (OTP) area

> Erase capability

-        Subsector (4-Kbyte) granularity

-        Sector (64-Kbyte) granularity

-        Bulk Erase (8 Mbit) in 8 s (typical)

> Write protections

-        Software write protection applicable to every 64-Kbyte sector (volatile lock bit)

-        Hardware write protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2)

> Deep Power-down mode: 5 μA (typical)

> Electronic signature

-        JEDEC standard two-byte signature (7114h)

-        Unique ID code (UID) with16 bytes read-only, available upon customer request

> More than 100 000 write cycles per sector

> More than 20 year data retention

> Packages

-        RoHS compliant

Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity)

Sector Lock Register		Protection status
Lock Down bit	Write Lock bit
0	0	Sector unprotected from Program/Erase/Write operations, protection status reversible
0	1	Sector protected from Program/Erase/Write operations, protection status reversible
1	0	Sector unprotected from Program/Erase/Write operations, Sector protection status cannot be changed except by a power-up.
1	1	Sector protected from Program/Erase/Write operations, Sector protection status cannot be changed except by a Power-up.

Instruction set

Instruction	Description	One-byte instruction code	Address Bytes	Dummy Bytes	Data Bytes
WREN	Write Enable	06h (0000 0110B)	0	0	0
WRDI	Write Disable	04h (0000 0100B)	0	0	0
RDID	Read Identification	9Fh (1001 1111B)	0	0	1 to 20
		9Eh (1001 1110B)	0	0	1 to 3
RDSR	Read Status Register	05h (0000 0101B)	0	0	1 to ∞
WRSR	Write Status Register	01h (0000 0001B)	0	0	1
WRLR	Write to Lock Register	E5h (1110 0101B)	3	0	1
RDLR	Read Lock Register	E8h (1110 1000B)	3	0	1
READ	Read Data Bytes	03h (0000 0011B)	3	0	1 to ∞
FAST_READ	Read Data Bytes at higher speed	0Bh (0000 1011B)	3	1	1 to ∞
DOFR	Dual Output Fast Read	3Bh (0011 1011B)	3	1	1 to ∞
ROTP	Read OTP (Read 64 bytes of OTP area)	4Bh (0100 1011B)	3	1	1 to 65
POTP	Program OTP (Program 64 bytes of OTP area)	42h (0100 0010B)	3	0	1 to 65
PP	Page Program	02h (0000 0010B)	3	0	1 to 256
DIFP	Dual Input Fast Program	A2h (1010 0010B)	3	0	1 to 256
SSE	Subsector Erase	20h (0010 0000B)	3	0	0
SE	Sector Erase	D8h (1101 1000B)	3	0	0
BE	Bulk Erase	C7h (1100 0111B)	0	0	0
DP	Deep Power-down	B9h (1011 1001B)	0	0	0
RDP	Release from Deep Power-down	ABh (1010 1011B)	0	0	0

 

Status Register Format

Bit	Name	Description
7	SRWD	Status Register Write Protect
6	0
5	TB	Top/Bottom bit
4:2	BP2 – BP0	Block Protect bits
1	WEL	Write Enable Latch bit
0	WIP	Write In Progress bit

Manufacturer and Device ID Information

Byte No.	Data Type	Value
1	Manufacturer identification	20h
2	Device identification (Memory type)	71h
3	Device identification (Memory capacity)	14h
4	UID(CFD length)	10h
5-20	UID(CFD content)	16 bytes