IO BAR 0 task
register for channel 0, 8byte
|
Address
|
Write/Read
|
register
|
Description
|
|
00
|
Write/Read
|
Data
|
Data port for PIO data transfer
|
|
01
|
Write
|
Features
|
Features register of the command input
|
|
01
|
Read
|
Error
|
Error register of the command output
|
|
02
|
Write/Read
|
Sector count
|
Sector count register of the command
|
|
03
|
Write/Read
|
LBA Low
|
LBA low for the command
|
|
04
|
Write/Read
|
LBA Mid
|
LBA mid for the command
|
|
05
|
Write/Read
|
LBA High
|
LBA high for the command
|
|
06
|
Write/Read
|
Device Head
|
Device Head register for the command
|
|
07
|
Write
|
Command
|
Operate code for the command
|
|
07
|
Read
|
Status
|
Status register for the command output
|
IO BAR 1 control
register for channel 0, 4 byte
|
Address
|
Write/Read
|
register
|
Description
|
|
00
|
Write/Read
|
reserved
|
Reserved
|
|
01
|
Write/Read
|
reserved
|
Reserved
|
|
02
|
Write
|
Control
|
Control register
|
|
02
|
Read
|
Alt-status
|
The Alt-Status register
|
|
03
|
Write/Read
|
Reserved
|
Reserved
|
IO BAR 2 task register
for channel 1, 8 byte
|
Address
|
Write/Read
|
register
|
Description
|
|
00
|
Write/Read
|
Data
|
Data port for PIO data transfer
|
|
01
|
Write
|
Features
|
Features register of the command input
|
|
01
|
Read
|
Error
|
Error register of the command output
|
|
02
|
Write/Read
|
Sector count
|
Sector count register of the command
|
|
03
|
Write/Read
|
LBA Low
|
LBA low for the command
|
|
04
|
Write/Read
|
LBA Mid
|
LBA mid for the command
|
|
05
|
Write/Read
|
LBA High
|
LBA high for the command
|
|
06
|
Write/Read
|
Device Head
|
Device Head register for the command
|
|
07
|
Write
|
Command
|
Operate code for the command
|
|
07
|
Read
|
Status
|
Status register for the command output
|
IO BAR 3 control
register for channel 1, 4 byte
|
Address
|
Write/Read
|
register
|
Description
|
|
00
|
Write/Read
|
reserved
|
Reserved
|
|
01
|
Write/Read
|
reserved
|
Reserved
|
|
02
|
Write
|
Control
|
Control register
|
|
02
|
Read
|
Alt-status
|
The Alt-Status register
|
|
03
|
Write/Read
|
Reserved
|
Reserved
|
IO BAR 4 bus master register, 16 byte
|
Address
|
Write/Read
|
Register
|
|
00
|
Write/Read
|
ATA Bus Maser Command register for
channel x
|
|
01
|
Write/Read
|
Device specific
|
|
02
|
Write/Read
|
ATA Bus Master Status register for
channel x
|
|
03
|
Write/Read
|
Device specific
|
|
04-07
|
Write/Read
|
ATA bus master PRD table address for
channel x
|
|
08
|
Write/Read
|
ATA Bus Maser Command register for channel y
|
|
09
|
Write/Read
|
Device specific
|
|
0a
|
Write/Read
|
ATA Bus Master Status register for
channel y
|
|
0b
|
Write/Read
|
Device specific
|
|
0c-0f
|
Write/Read
|
ATA bus master PRD table address for
channel y
|
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