IDE Related Registers

Offset from Base address	Register	Register access
00h	Bus Master IDE Command register	R/W
	Primary
01h	Device Specific
02h	Bus Master IDE Status register	RWC
	Primary
03h	Device Specific
04h-07h	Bus Master IDE PRD Table address	R/W
	Primary
08h	Bus Master IDE Command register	R/W
	Secondary
09h	Device Specific
0Ah	Bus Master IDE Status register	RWC
	Secondary
0Bh	Device Specific
0Ch-0Fh	Bus Master IDE PRD Table address	R/W
	Secondary

Bit	Description
7:4	Reserved. Return 0.
3	Read/Write Control(RWC) – R/W
2:1	Reserved. Return 0.
0	Start/Stop Bus Master(START) – R/W

Bus Master IDE Command Register

Bit	Description
7	PRD Interrupt Status(PRDIS) – R/WC.
6	Drive 1 DMA Capable – R/W.
5	Drive 0 DMA Capable – R/W.
4:3	Reserved. Return 0.
2	Interrupt – R/WC.
1	Error – R/WC.
0	Bus Master IDE Active(Act) – RO.

Bus Master IDE Status Register

Bit	Description
31:2	Address of Descriptor Table(ADDR) – R/W.
1:0	Reserved

Bus Master IDE Descriptor Table Pointer Register